Volume : 7, Issue : 1, January - 2018

A Bus Encoding Technique for Minimizing Delay in VLSI Interconnects

Tanu Verma

Abstract :

<p>&nbsp;</p> <p class="MsoNormalCxSpFirst" style="text-align:justify;text-justify:inter-ideograph"><b style="mso-bidi-font-weight:normal"><span style="mso-bidi-font-size:9.0pt;&#10;color:black">In a typical bus system of NOC</span><span style="color:black">, </span></b><b style="mso-bidi-font-weight:normal"><span style="mso-fareast-font-family:Calii">crosstalk can affect signal delays by changing the times at which signal transitions occur.</span><span style="color:black"> Hence, Delay reduction</span></b><b style="mso-bidi-font-weight:normal"><span style="mso-bidi-font-size:9.0pt;&#10;color:black"> is main objective of our current research work. This paper develops a novel technique, in which inter-wire crosstalk considers sufficiently and reduces the delay due to coupling transition approximately up to </span>13% - 13.63% for 8 bit, 16 bit, 32 bit and 64 bit wide data bus with an additional area penalty<span style="color:black">.</span></b><b style="mso-bidi-font-weight:normal"><span style="mso-bidi-font-size:9.0pt;&#10;color:black"> The effectiveness of coding method has been tested using MATLAB. Transmission results are tested on bus of network on chip which is simulated on Xilinx and implemented on FPGA.</span></b><span style="font-size:9.0pt"><o:p></o:p></span></p>